NetMac.hpp

//------------------------------------------------------------------------------
//This file is part of embKernel. 
//See license.txt for the full license governing this code.
//------------------------------------------------------------------------------

#ifndef NET_MAC_STM32F4XX_HPP_
#define NET_MAC_STM32F4XX_HPP_

#include "RtosSemaphore.hpp"
#include "NetDefs.hpp"

class NetMac {
    friend class Net;
public:
    NetMac();

    static const int EMAC_RX_FRAG_COUNT = 4;
    static const int EMAC_TX_FRAG_COUNT = 8;
private:
    //Phy registers
    const static uint32_t PHY_REG_BMCR = 0x00; // Basic Mode Control Register
    const static uint32_t PHY_REG_BMSR = 0x01; // Basic Mode Status Register
    const static uint32_t PHY_REG_IDR1 = 0x02; // PHY Identifier 1
    const static uint32_t PHY_REG_IDR2 = 0x03; // PHY Identifier 2
    const static uint32_t PHY_REG_ANAR = 0x04; // Auto-Negotiation Advertisement
    const static uint32_t PHY_REG_ANLPAR = 0x05; // Auto-Neg. Link Partner Abitily
    const static uint32_t PHY_REG_ANER = 0x06; // Auto-Neg. Expansion Register
    const static uint32_t PHY_REG_ANNPTR = 0x07; // Auto-Neg. Next Page TX
    const static uint32_t PHY_REG_LPNPA = 0x08; //

    //Basic Mode Control Register bits
    const static uint32_t PHY_BMCR_RESET = (1 << 15); // Reset bit
    const static uint32_t PHY_BMCR_LOOPBACK = (1 << 14); // Loop back
    const static uint32_t PHY_BMCR_SPEED_SEL = (1 << 13); // Speed selection
    const static uint32_t PHY_BMCR_AN = (1 << 12); // Auto Negotiation
    const static uint32_t PHY_BMCR_POWERDOWN = (1 << 11); // Power down mode
    const static uint32_t PHY_BMCR_ISOLATE = (1 << 10); // Isolate
    const static uint32_t PHY_BMCR_RE_AN = (1 << 9); // Restart auto negotiation
    const static uint32_t PHY_BMCR_DUPLEX = (1 << 8); // Duplex mode

    //Basic Mode Status Register bits
    const static uint32_t PHY_BMSR_100BE_T4 = (1 << 15); // 100 base T4
    const static uint32_t PHY_BMSR_100TX_FULL = (1 << 14); // 100 base full duplex
    const static uint32_t PHY_BMSR_100TX_HALF = (1 << 13); // 100 base half duplex
    const static uint32_t PHY_BMSR_10BE_FULL = (1 << 12); // 10 base T full duplex
    const static uint32_t PHY_BMSR_10BE_HALF = (1 << 11); // 10 base T half duplex
    const static uint32_t PHY_BMSR_NOPREAM = (1 << 6); // MF Preamable Supress
    const static uint32_t PHY_BMSR_AUTO_DONE = (1 << 5); // Auto negotiation complete
    const static uint32_t PHY_BMSR_REMOTE_FAULT = (1 << 4); // Remote fault
    const static uint32_t PHY_BMSR_NO_AUTO = (1 << 3); // Auto Negotiation ability
    const static uint32_t PHY_BMSR_LINK_ESTABLISHED = (1 << 2); // Link status

    const static uint32_t RX_DESC0_OWN = 0x80000000; // OWN bit: descriptor is owned by DMA engine
    const static uint32_t RX_DESC0_AFM = 0x40000000; // DA Filter Fail for the rx frame
    const static uint32_t RX_DESC0_FL = 0x3FFF0000; // Receive descriptor frame length
    const static uint32_t RX_DESC0_ES = 0x00008000; // Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE
    const static uint32_t RX_DESC0_DE = 0x00004000; // Descriptor error: no more descriptors for receive frame
    const static uint32_t RX_DESC0_SAF = 0x00002000; // SA Filter Fail for the received frame
    const static uint32_t RX_DESC0_LE = 0x00001000; // Frame size not matching with length field
    const static uint32_t RX_DESC0_OE = 0x00000800; // Overflow Error: Frame was damaged due to buffer overflow
    const static uint32_t RX_DESC0_VLAN = 0x00000400; // VLAN Tag: received frame is a VLAN frame
    const static uint32_t RX_DESC0_FS = 0x00000200; // First descriptor of the frame
    const static uint32_t RX_DESC0_LS = 0x00000100; // Last descriptor of the frame
    const static uint32_t RX_DESC0_IPV4HCE = 0x00000080; // IPC Checksum Error: Rx Ipv4 header checksum error
    const static uint32_t RX_DESC0_LC = 0x00000040; // Late collision occurred during reception
    const static uint32_t RX_DESC0_FT = 0x00000020; // Frame type - Ethernet, otherwise 802.3
    const static uint32_t RX_DESC0_RWT = 0x00000010; // Receive Watchdog Timeout: watchdog timer expired during reception
    const static uint32_t RX_DESC0_RE = 0x00000008; // Receive error: error reported by MII interface
    const static uint32_t RX_DESC0_DBE = 0x00000004; // Dribble bit error: frame contains non int multiple of 8 bits
    const static uint32_t RX_DESC0_CE = 0x00000002; // CRC error
    const static uint32_t RX_DESC0_MAMPCE = 0x00000001; // Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error

    const static uint32_t TX_DESC0_OWN = 0x80000000; //OWN bit: descriptor is owned by DMA engine
    const static uint32_t TX_DESC0_IC = 0x40000000; //Interrupt on Completion
    const static uint32_t TX_DESC0_LS = 0x20000000; //Last Segment
    const static uint32_t TX_DESC0_FS = 0x10000000; //First Segment
    const static uint32_t TX_DESC0_DC = 0x08000000; //Disable CRC
    const static uint32_t TX_DESC0_DP = 0x04000000; //Disable Padding
    const static uint32_t TX_DESC0_TTSE = 0x02000000; //Transmit Time Stamp Enable
    const static uint32_t TX_DESC0_CIC = 0x00C00000; //Checksum Insertion Control: 4 cases
    const static uint32_t TX_DESC0_CIC_ByPass = 0x00000000; //Do Nothing: Checksum Engine is bypassed
    const static uint32_t TX_DESC0_CIC_IPV4Header = 0x00400000; //IPV4 header Checksum Insertion
    const static uint32_t TX_DESC0_CIC_TCPUDPICMP_Segment = 0x00800000; //TCP/UDP/ICMP Checksum Insertion calculated over segment only
    const static uint32_t TX_DESC0_CIC_TCPUDPICMP_Full = 0x00C00000; //TCP/UDP/ICMP Checksum Insertion fully calculated
    const static uint32_t TX_DESC0_TER = 0x00200000; //Transmit End of Ring
    const static uint32_t TX_DESC0_TCH = 0x00100000; //Second Address Chained
    const static uint32_t TX_DESC0_TTSS = 0x00020000; //Tx Time Stamp Status
    const static uint32_t TX_DESC0_IHE = 0x00010000; //IP Header Error
    const static uint32_t TX_DESC0_ES = 0x00008000; //Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT
    const static uint32_t TX_DESC0_JT = 0x00004000; //Jabber Timeout
    const static uint32_t TX_DESC0_FF = 0x00002000; //Frame Flushed: DMA/MTL flushed the frame due to SW flush
    const static uint32_t TX_DESC0_PCE = 0x00001000; //Payload Checksum Error
    const static uint32_t TX_DESC0_LCA = 0x00000800; //Loss of Carrier: carrier lost during transmission
    const static uint32_t TX_DESC0_NC = 0x00000400; //No Carrier: no carrier signal from the transceiver
    const static uint32_t TX_DESC0_LCO = 0x00000200; //Late Collision: transmission aborted due to collision
    const static uint32_t TX_DESC0_EC = 0x00000100; //Excessive Collision: transmission aborted after 16 collisions
    const static uint32_t TX_DESC0_VF = 0x00000080; //VLAN Frame
    const static uint32_t TX_DESC0_CC = 0x00000078; //Collision Count
    const static uint32_t TX_DESC0_ED = 0x00000004; //Excessive Deferral
    const static uint32_t TX_DESC0_UF = 0x00000002; //Underflow Error: late data arrival from the memory
    const static uint32_t TX_DESC0_DB = 0x00000001; //Deferred Bit

    typedef struct {
        union {
            uint32_t value;
            struct {
                uint32_t RMAM_PCE :1; //Payload checksum error / extended status available
                uint32_t CE :1; //CRC error
                uint32_t DE :1; //Dribble bit error
                uint32_t RE :1; //Receive error
                uint32_t RWT :1; //Receive watchdog timeout
                uint32_t FT :1; //Frame type
                uint32_t LC :1; //Late collision
                uint32_t IPHCE :1; //IPv header checksum error / time stamp valid
                uint32_t LS :1; //Last descriptor
                uint32_t FS :1; //First descriptor
                uint32_t VLAN :1; //VLAN tag
                uint32_t OE :1; //Overflow error
                uint32_t LE :1; //Length error
                uint32_t SAF :1; //Source address filter fail
                uint32_t DERR :1; //Descriptor error
                uint32_t ES :1; //Error summary
                uint32_t FL :14; //Frame length
                uint32_t AFM :1; //Destination address filter fail
                uint32_t OWN :1; //Own bit, 1 when owned by DMA, 0 otherwise
            } bits;
        } rdes0;
        union {
            uint32_t value;
            struct {
                uint32_t RBS1 :13; //Receive buffer 1 size
                uint32_t :1; //Reserved, must be kept at reset value.
                uint32_t RCH :1; //Second address chained
                uint32_t RER :1; //Receive end of ring
                uint32_t RBS2 :13; //Receive buffer 2 size
                uint32_t :2; //Reserved, must be kept at reset value.
                uint32_t DIC :1; //Disable interrupt on completion
            } bits;
        } rdes1;
        uint32_t rdes2;
        uint32_t rdes3;
    }__attribute__((packed)) RX_DESC;

    typedef enum uint8_t {
        TX_FRAG_NO_BUFFER = 0,
        TX_FRAG_DISCARDABLE,
        TX_FRAG_NOT_DISCARDABLE
    } TX_FRAG_STATE;

    typedef struct {
        union {
            uint32_t value;
            struct {
                uint32_t DB :1; //Deferred bit
                uint32_t UF :1; //Underflow error
                uint32_t ED :1; //Excessive deferral
                uint32_t CC :4; //Collision count
                uint32_t VF :1; //VLAN frame
                uint32_t EC :1; //Excessive collision
                uint32_t LC :1; //Late collision
                uint32_t NC :1; //No carrier
                uint32_t LSC :1; //Loss of carrier
                uint32_t IPE :1; //IP payload error
                uint32_t FF :1; //Frame flushed
                uint32_t JT :1; //Jabber timeout
                uint32_t ES :1; //Error summary
                uint32_t IHE :1; //IP header error
                uint32_t TTSS :1; //Transmit time stamp status
                uint32_t Res1 :2; //Reserved, must be kept at reset value.
                uint32_t TCH :1; //Second address chained
                uint32_t TER :1; //Transmit end of ring
                uint32_t CIC :2; //Checksum insertion control
                uint32_t Res2 :1; //Reserved, must be kept at reset value.
                uint32_t TTSE :1; //Transmit time stamp enable
                uint32_t DP :1; //Disable pad
                uint32_t DC :1; //Disable CRC
                uint32_t FS :1; //First segment
                uint32_t LSEG :1; //Last segment
                uint32_t IC :1; //Interrupt on completion
                uint32_t OWN :1; //Own bit, 1 when owned by DMA, 0 otherwise
            } bits;
        } tdes0;
        union {
            uint32_t value;
            struct {
                uint32_t TBS1 :13; //TBS1: Transmit buffer 1 size
                uint32_t Res1 :3; //Reserved, must be kept at reset value.
                uint32_t TBS2 :12; //Transmit buffer 2 size
                uint32_t Res2 :3; //Reserved, must be kept at reset value.
            } bits;
        } tdes1;
        uint32_t tdes2;
        uint32_t tdes3;
        TX_FRAG_STATE state;
        uint8_t spare[3];
    }__attribute__((packed)) TX_DESC;

    __attribute__ ((aligned (4))) RX_DESC sRxDesc[EMAC_RX_FRAG_COUNT];
    __attribute__ ((aligned (4))) TX_DESC sTxDesc[EMAC_TX_FRAG_COUNT];

    int sTxNextToSend;
    int sTxNextToCheck;

    int mRxIdx;

    NetDefs::MAC_ADDR sAddr;

    bool phyWrite(uint16_t reg, uint16_t value);
    uint32_t phyRead(uint16_t reg);

    RtosSemaphore mSema;

    uint32_t mPhyId;

    uint16_t mPhyAddr;

private:
    void start(const NetDefs::MAC_ADDR& addr);
    NetDefs::FRAME* getFrame();
    void putHeader(NetDefs::FRAME& frame, const NetDefs::MAC_ADDR& dst, NetDefs::MAC_TYPE type);
    bool flush(NetDefs::FRAME& frame, size_t len, bool discardable);
    void freeSentFrames();
};

#endif /* NET_MAC_STM32F4XX_HPP_ */