Hw.cpp

//------------------------------------------------------------------------------
//This file is part of embKernel. 
//See license.txt for the full license governing this code.
//------------------------------------------------------------------------------

#include "Hw.hpp"
#include "stm32f30x.h"

DrvGpio Hw::sLed3;
DrvGpio Hw::sLed4;
DrvGpio Hw::sLed5;
DrvGpio Hw::sLed6;
DrvGpio Hw::sLed7;
DrvGpio Hw::sLed8;
DrvGpio Hw::sLed9;
DrvGpio Hw::sLed10;
DrvI2cMaster Hw::sI2cLsm303dlhc;
LSM303DLHC Hw::sLsm303dlhc(&sI2cLsm303dlhc);

void Hw::init() {
    //Clock configuration.
    //PLLCLK=72MHz, SYSCLK=72MHz, HCLK=72MHz, APB1CLK=36MHz, APB2CLK=72MHz
    RCC ->CFGR = 0; //Reset all clock config

    RCC ->CR |= ((uint32_t) RCC_CR_HSEON ); //Enable HSE

    while (!(RCC ->CR & RCC_CR_HSERDY )) { //Wait HSE ready
    }

    FLASH ->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1; //  Prefetch Buffer Enable, Flash 2 wait state

    RCC ->CFGR = RCC_CFGR_HPRE_DIV1 | //HLCK prescaler = 1 (72MHz)
            RCC_CFGR_PPRE2_DIV1 | //APB high-speed prescaler  = 1 (72MHz)
            RCC_CFGR_PPRE1_DIV2 | //APB low-speed prescaler  = 2 (36MHz)
            RCC_CFGR_PLLSRC_PREDIV1 | //HSE/PREDIV selected as PLL input clock
            RCC_CFGR_PLLXTPRE_PREDIV1 | //HSE input to PLL not divided
            RCC_CFGR_PLLMULL9; //PLL multiplication factor = 9 (72MHz)

    RCC ->CFGR2 = RCC_CFGR2_ADCPRE12_DIV1 | RCC_CFGR2_ADCPRE34_DIV1;
    RCC ->CR |= ((uint32_t) RCC_CR_PLLON ); //Enable PLL

    while (!(RCC ->CR & RCC_CR_PLLRDY )) { //Wait PLL ready
    }

    RCC ->CFGR |= RCC_CFGR_SW_PLL; //Switch to PLL clock

    while (!(RCC ->CFGR & RCC_CFGR_SWS_PLL )) { //Wait for system to switch to PLL
    }

    RCC ->CFGR3 = RCC_CFGR3_TIM1SW | RCC_CFGR3_TIM8SW; //Clock source for TIM1 and TIM8 is PLLCLK x 2

    //Enable peripherals
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); // set CP10 and CP11 Full Access
#endif

    RCC ->AHBENR = //RCC_AHBENR_DMA1EN | // DMA1 clock enable
    //RCC_AHBENR_DMA2EN | // DMA2 clock enable
    //RCC_AHBENR_SRAMEN | // SRAM interface clock enable
    //RCC_AHBENR_FLITFEN | // FLITF clock enable
    //RCC_AHBENR_CRCEN | // CRC clock enable
    RCC_AHBENR_GPIOAEN | // GPIOA clock enable
            RCC_AHBENR_GPIOBEN | // GPIOB clock enable
            RCC_AHBENR_GPIOCEN | // GPIOC clock enable
            RCC_AHBENR_GPIODEN | // GPIOD clock enable
            RCC_AHBENR_GPIOEEN | // GPIOE clock enable
            RCC_AHBENR_GPIOFEN; // | // GPIOF clock enable
    //RCC_AHBENR_TSEN | // TS clock enable
    //RCC_AHBENR_ADC12EN | // ADC1/ ADC2 clock enable
    //RCC_AHBENR_ADC34EN; // ADC1/ ADC2 clock enable

    RCC ->APB1ENR = //RCC_APB1ENR_TIM2EN | // Timer 2 clock enable
    //RCC_APB1ENR_TIM3EN | // Timer 3 clock enable
    //RCC_APB1ENR_TIM4EN | // Timer 4 clock enable
    //RCC_APB1ENR_TIM6EN | // Timer 6 clock enable
    //RCC_APB1ENR_TIM7EN | // Timer 7 clock enable
    //RCC_APB1ENR_WWDGEN | // Window Watchdog clock enable
    //RCC_APB1ENR_SPI2EN | // SPI2 clock enable
    //RCC_APB1ENR_SPI3EN | // SPI3 clock enable
    //RCC_APB1ENR_USART2EN | // USART 2 clock enable
    //RCC_APB1ENR_USART3EN | // USART 3 clock enable
    //RCC_APB1ENR_UART3EN | // UART 3 clock enable
    //RCC_APB1ENR_UART4EN | // UART 4 clock enable
    RCC_APB1ENR_I2C1EN | // I2C 1 clock enable
            //RCC_APB1ENR_I2C2EN | // I2C 2 clock enable
            RCC_APB1ENR_USBEN | // USB clock enable
            //RCC_APB1ENR_CAN1EN | // CAN clock enable
            RCC_APB1ENR_PWREN; // | // PWR clock enable
    //RCC_APB1ENR_DACEN; // DAC clock enable

    RCC ->APB2ENR = RCC_APB2ENR_SYSCFGEN; // | // SYSCFG clock enable
    //RCC_APB2ENR_TIM1EN | // TIM1 clock enable
    //RCC_APB2ENR_SPI1EN | // SPI1 clock enable
    //RCC_APB2ENR_TIM8EN | // TIM8 clock enable
    //RCC_APB2ENR_USART1EN; // | // USART1 clock enable
    //RCC_APB2ENR_TIM15EN | // TIM15 clock enable
    //RCC_APB2ENR_TIM16EN | // TIM16 clock enable
    //RCC_APB2ENR_TIM17EN // TIM17 clock enable

    DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL); //USB D+

    sLed3.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN9, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed4.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN8, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed5.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN10, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed6.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN15, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed7.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN11, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed8.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN14, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed9.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
    sLed10.init(DrvTypes::DRV_PORTE, DrvTypes::DRV_PIN13, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);

    DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN11, DrvTypes::DRV_FUNC14, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //USB D-
    DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC14, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //USB D+

    sI2cLsm303dlhc.init(DrvTypes::DRV_I2C1);
    DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTB, DrvTypes::DRV_PIN6, DrvTypes::DRV_FUNC4, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //Lsm303dlhc SCL
    DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTB, DrvTypes::DRV_PIN7, DrvTypes::DRV_FUNC4, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //Lsm303dlhc SDA
}