embkernel
 All Classes Functions Variables Typedefs Groups Pages
Hw.cpp
1 //------------------------------------------------------------------------------
2 //This file is part of embKernel.
3 //See license.txt for the full license governing this code.
4 //------------------------------------------------------------------------------
5 
6 #include "Hw.hpp"
7 #include "stm32f4xx.h"
8 
9 DrvGpio Hw::sButton;
10 DrvGpio Hw::sLed1;
11 DrvGpio Hw::sLed2;
12 DrvGpio Hw::sLed3;
13 DrvGpio Hw::sLed4;
14 
15 void Hw::init() {
17  //Clock config
19  RCC ->CFGR = 0; //Reset all clock config
20 
21  RCC ->CR = RCC_CR_HSION | RCC_CR_HSEON | PWR_CR_VOS; //HSI and HSE on, Regulator voltage=1 (maximum frequency)
22 
23  while (!(RCC ->CR & RCC_CR_HSERDY )) { //Wait HSE ready
24  }
25 
26  FLASH ->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; //6 wait states, data and instruction cache enabled
27 
28  const static uint32_t PLLM = 4;
29  const static uint32_t PLLN = 168;
30  const static uint32_t PLLQ = 7;
31  const static uint32_t PLLP = 2;
32  RCC ->PLLCFGR = PLLM | RCC_PLLCFGR_PLLSRC_HSE | (PLLN << 6) | (PLLQ << 24) | (((PLLP >> 1) - 1) << 16);
33 
34  RCC ->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2; //SYSCLK=168MHz, APB1=42MHz,APB2=84MHz
35 
36  RCC ->CR |= RCC_CR_PLLON; //Enable PLL
37 
38  while (!(RCC ->CR & RCC_CR_PLLRDY )) { //Wait PLL ready
39  }
40 
41  RCC ->CFGR |= RCC_CFGR_SW_PLL; //Switch to PLL clock
42 
43  while (!(RCC ->CFGR & RCC_CFGR_SWS_PLL )) { //Wait for system to switch to PLL
44  }
45 
47  //Enable peripherals
49 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
50  SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
51 #endif
52 
53  RCC ->AHB1ENR |= RCC_APB1ENR_PWREN | RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | //
54  RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | //
55  RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN | //
56  RCC_AHB1ENR_DMA2EN;
57 
58  RCC ->APB1ENR |= RCC_APB1ENR_SPI2EN;
59  RCC ->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_SDIOEN | RCC_APB2ENR_SPI1EN;
60 
61  SYSCFG ->PMC |= SYSCFG_PMC_MII_RMII_SEL; //Set RMII mode
62 
64  //Ethernet RMII
66  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN1, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_REF_CLK
67  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN2, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //MDIO
68  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTA, DrvTypes::DRV_PIN7, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_CRS_DV
69 
70  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTB, DrvTypes::DRV_PIN11, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_TX_EN
71  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTB, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_TXD0
72  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTB, DrvTypes::DRV_PIN13, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_TXD1
73 
74  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN1, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //MDC
75  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN4, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_RXD0
76  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN5, DrvTypes::DRV_FUNC11, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //RMII_RXD1
77 
79  //SDIO
81  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN7, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_INPUT, DrvTypes::PUPD_PULL_UP); //SD DETECT
82  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN8, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION, DrvTypes::PUPD_PULL_UP); //SDIO_D0
83  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN9, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION, DrvTypes::PUPD_PULL_UP); //SDIO_D1
84  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN10, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION, DrvTypes::PUPD_PULL_UP); //SDIO_D2
85  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN11, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION, DrvTypes::PUPD_PULL_UP); //SDIO_D3
86  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTC, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION); //SDIO_CK
87  DrvGpio::setPinFuncMode(DrvTypes::DRV_PORTD, DrvTypes::DRV_PIN2, DrvTypes::DRV_FUNC12, DrvTypes::DRV_MODE_ALTERNATE_FUNCTION, DrvTypes::PUPD_PULL_UP); //SDIO_CMD
88 
90  //LED
92  sLed1.init(DrvTypes::DRV_PORTD, DrvTypes::DRV_PIN12, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
93  sLed2.init(DrvTypes::DRV_PORTD, DrvTypes::DRV_PIN13, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
94  sLed3.init(DrvTypes::DRV_PORTD, DrvTypes::DRV_PIN14, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
95  sLed4.init(DrvTypes::DRV_PORTD, DrvTypes::DRV_PIN15, DrvTypes::DRV_FUNC0, DrvTypes::DRV_MODE_OUTPUT_PUSH_PULL);
96 
97 }